Samsung Researchers Publish Ultra-Low-Power NAND Flash Innovation in Nature
As AI technology expands, the role of storage, responsible for storing and processing ever-growing volumes of data, has become more critical than ever. Consequently, while there is an escalating demand for higher capacity and efficiency, conventional NAND flash architectures face a structural limitation: power consumption inevitably increases as the number of stacked layers grows.
A newly published study from Samsung Advanced Institute of Technology (SAIT) presents a breakthrough solution to this challenge. By integrating ferroelectric* with oxide semiconductors*, the research team identified a mechanism that reduces power consumption in string-level operation* by up to 96% compared with existing technology.
* Ferroelectric: Materials that can store information with spontaneous polarization
* Oxide semiconductors: Channel materials that offer ultra-low leakage current, overcoming silicon’s limitations.
* String-level operation: The method by which NAND flash reads/writes data by passing signals through series-connected cells.
The achievement is the result of extensive internal collaboration, featuring 34 researchers from SAIT and Samsung’s Semiconductor R&D Center as co-authors. The findings were published in the latest online edition of the prestigious journal Nature, titled “Ferroelectric transistors for low-power NAND flash memory.”
Turning a Weakness into an Asset: The Oxide Semiconductor Breakthrough
Conventional NAND stores data by injecting electrons into memory cells. To increase storage density, manufacturers must increase the number of stacked layers. However, because signals must pass sequentially through cells connected in series, taller stacks lead to significantly increased read/write power consumption. While ferroelectric-based concepts have been proposed previously, the trade-off between capacity scaling and power efficiency remained unresolved.
Samsung researchers discovered the solution within the unique electrical characteristics of oxide semiconductors.
Traditionally, certain characteristics of this material, such as restricted threshold voltage* tunability, were considered disadvantageous for high-performance devices. However, in a ferroelectric-based NAND structure, this property becomes a strength, enabling dramatic reductions in power consumption.
* Threshold voltage: The voltage level at which a transistor begins to turn on
By harnessing these properties and integrating them into a ferroelectric NAND structure, the team defined the world’s first mechanism enabling up to 96% reduction in power during cell-string operation, while still supporting industry-leading density of up to 5 bits per cell.
A limitation of conventional NAND architectures has been transformed into a new opportunity through advanced material development and structural innovation.
Paving the Way for Ultra-Low-Power Storage, from Data Centers to Mobile
Once commercialized, this technology is expected to significantly enhance power efficiency across a wide range of applications—from large-scale AI data centers to mobile and edge-AI systems. Lower power consumption can help reduce operating costs in data centers, while extending battery life in mobile devices.
“We are proud to have verified the feasibility of ultra-low-power NAND flash. As storage plays an increasingly critical role in the AI ecosystem, we will continue follow-up research with the goal of applying this technology to future products,” said Dr. Sijung Yoo, the first author of the paper.
As demands on storage devices in the AI era continue to grow, this research marks a meaningful step toward the next stage of storage innovation, with continued advancement expected through future research.
