Breaking Through the Limits of Horizontal Scaling with Vertical Innovation
Samsung Semiconductor R&D Center Demonstrates Industry’s First
42nm Gate-Pitch 3D-Stacked Transistor
Selected as the Best Paper from over 1,000 submissions to the 2026 VLSI Symposium
with a highest review score
Samsung Semiconductor R&D Center’s Logic TD Team has demonstrated the industry’s first 3D Stacked FET (Field-Effect Transistor[1]) architecture with a 42nm gate pitch[2], a milestone unveiled at the VLSI Symposium, one of the world’s leading semiconductor conferences.
The research selected as the Technology Highlight at the 2026 VLSI Symposium and has attracted industry attention as a structural breakthrough that overcomes the physical limits of horizontal transistor scaling.
From V-NAND to HBM, and Now: Logic Joins the Vertical Era
Three-dimensional integration has already transformed the memory industry. V-NAND in Flash and HBM in DRAM have overcome density limitations through vertically integrated architectures. The research team explains that expanding this technology to logic chips was the next logical step.
Q. What inspired the team to pivot toward 3D transistor structures?
“We see this as a natural evolution. Looking back at the history of device scaling, vertically integrated architectures have overcome the limitations of area scaling. V-NAND in Flash memory and HBM in DRAM are among the most notable examples. It was only a matter of time before this evolution extended to logic device development as well.”
— WookHyun Kwon, Master, Logic Technology Development Team, Samsung Electronics Semiconductor R&D Center
Transistors as High-Rises: Confronting the Physical Limits of 2D Layouts
For logic chips (like CPUs and GPUs that handle computation and control), the primary demand from customers is simple: maximize transistor density per unit area. As transistors are placed closer together, however, the insulating layers that electrically isolate adjacent devices must also become thinner. Once those layers reach their physical limits, electrical interference between devices becomes unavoidable. This fundamental constraint has long been one of the key barriers to further horizontal scaling.
Q. What were the bottlenecks of existing transistor technology?
“If memory chips are like fast food, logic chips are like fine dining. Logic customers require highly customized solutions, and one of their biggest demands today is increasing the number of transistors per unit area.
The problem is that when you push transistors too close together, the insulating barrier thins out to the point where it fails to block current, causing the chip to malfunction.
Vertical integration removes that horizontal insulation bottleneck. Instead of placing two devices side by side, we stack them on top of each other. It is similar to replacing a dense neighborhood of single-family homes with multi-story apartment buildings that make more efficient use of limited land.”
— YOUNGCHAI JUNG, TL, Logic Technology Development Team, Samsung Electronics Semiconductor R&D Center
2D vs. 3D: The Architecture Behind Doubling Density
In horizontal structures, insulator thickness directly affects the lateral spacing between devices. In a vertical layout, the insulator separating the upper and lower transistors is defined in the vertical direction, completely independent of horizontal area. In theory, this enables packing twice as many devices into the same surface area.
Q. How is a 3D transistor structurally different from a 2D transistor, and how does it impact performance?
“A 2D device expands laterally, while a 3D transistor is stacked vertically. Horizontal scaling faces a hard stop due to the minimum thickness of the isolation layers between adjacent transistors.
In contrast, the isolation layer between the upper and lower devices in a 3D structure is vertical and therefore does not consume additional surface area. Theoretically, reducing the area required for two devices down to the size of one doubles the integration density for the same footprint.”
— YOUNGCHAI JUNG, TL, Logic Technology Development Team, Samsung Electronics Semiconductor R&D Center
42nm: Setting a New Industry Benchmark
Prior to this publication, the industry’s smallest reported gate pitch was 48nm. The research team reduced it to 42nm, establishing a new benchmark for logic transistor scaling.
Q. What is the technological significance of a 42nm gate pitch?
“Gate pitch refers to the center-to-center spacing between adjacent transistor gates. Until our paper, the smallest reported gate pitch was 48nm. The 42nm gate pitch we demonstrated is the smallest ever reported for a physically fabricated transistor structure in the industry.
Beyond transistor scaling, we also achieved a nanosheet channel stack configuration with three upper and three lower nanosheet layers (3/3 stacks), surpassing the previous 2/2-stack structure. In addition, we were the first in the industry to connect these upper and lower devices using a direct vertical ‘I’-shaped interconnect known as RBC (RX Bounded Contact).”
— WookHyun Kwon, Master, Logic Technology Development Team, Samsung Electronics Semiconductor R&D Center
The Biggest Challenge: Etching and Filling Deep, Narrow Features
As vertical integration increases, so does the aspect ratio[3] of the structures, making etching processes significantly more difficult. The greatest technical challenge in this research was implementing the RBC[4] process, which requires creating direct vertical connections between upper and lower transistors through deep and narrow features.
Q. What was the most difficult technical challenge when the project began?
“With a vertically stacked structure, aspect ratios increase dramatically. Imagine trying to excavate a narrow gap between two skyscrapers. On top of that, filling that narrow, deep trench with dielectrics or metals without leaving voids is incredibly difficult.
Conventional methods used a ‘wrap-around contact’ that routed connections sideways in a ‘C’ shape. Our new RBC method, however, punches straight through vertically in an ‘I’ shape. This requires digging three times deeper, which elevates the process complexity to an entirely different level.”
— Donghoon Hwang,Logic Technology Development Team, Samsung Electronics Semiconductor R&D Center
Ten Days of Chuseok Holidays: The Whole Team Stayed at Their Posts
To meet the submission schedule for the 2026 VLSI Symposium, the team needed to complete development of the RBC process by October 2025.
Coincidentally, that month included Korea’s Chuseok holiday period, which offered up to ten consecutive days off. Rather than slowing development, the team organized around-the-clock support to maintain progress.
Q. Looking back on the project, was there a particular moment that became a turning point?
“Team members drafted their own work schedules to make sure no day went uncovered, voluntarily giving up vacations. The advanced process development team also stepped up by forming an emergency support task force.
I remember a newlywed engineer from the etch team who rescheduled her visits with in-laws just to come in and resolve a critical issue. Our lead author, Donghoon Hwang, came in throughout the entire holiday to personally track the progress of RBC development.
At one point, we tried a novel process using an new HM material, but the physical wafer testing didn’t yield the results we hoped for. We had to completely pivot our strategy on the fly. After four rounds of experimentation, we finally identified the optimal process. The collective experience of our process engineers, who had previously tackled vertical scaling in Flash and DRAM, served as our foundation. It was a defining moment of One Team spirit overcoming a crisis.”
— YOUNGCHAI JUNG, TL, Logic Technology Development Team, Samsung Electronics Semiconductor R&D Center
Doubling Power Efficiency and Performance for the AI Era
The Logic TD Team believes vertically stacked transistor architectures have the potential to deliver a step-change in both power efficiency and computing performance compared with generational transistor scaling.
Q. What benefits could this technology bring to future industries such as AI and high-performance computing (HPC), where power efficiency and performance are critical?
“Power efficiency is strongly influenced by the number of transistors that can be integrated within a given area. By adopting a vertically stacked architecture, the transistor count per unit area can be doubled, which in turn can theoretically improve power efficiency by up to 2x.
Conventional node-to-node scaling typically delivers performance improvements of around 15%. However, because 3D stacking instantaneously doubles the transistor density, it theoretically offers up to a 2x increase in transistor density.
We are certain this is the ideal architecture for the AI era, where clients demand logic chips that handle heavier compute workloads in smaller footprints with lower power consumption.”
— Donghoon Hwang, Logic Technology Development Team, Samsung Electronics Semiconductor R&D Center
Why Academia and Industry Take Notice
The research attracted significant attention from both academia and industry, ultimately earning the Best Paper Award at the 2026 VLSI Symposium.
Q. Why do you think this research received such high praise from both academic and industrial circles?
“We proved we could build the industry’s smallest gate-pitch transistor structure and stack it vertically for the first time. Beyond the dimensions, we successfully engineered a world-class triple-stacked nanosheet channel configuration for both upper and lower devices, and introduced the world’s first direct vertical connection via RBC. It was the combination of these technological achievements that earned this recognition.”
— WookHyun Kwon, Master, Logic Technology Development Team, Samsung Electronics Semiconductor R&D Center
Q. How would you summarize this achievement in one sentence, and why should the tech world pay attention?
“The essence of this research is overcoming the scaling limitations of horizontal device architectures through vertical integration.
By stacking two transistors within the footprint previously occupied by one, we demonstrated a structure capable of delivering twice the transistor density in the same area. It is an innovation worth paying close attention to.”
— YOUNGCHAI JUNG, TL, Logic Technology Development Team, Samsung Electronics Semiconductor R&D Center
Up Next: Ring Oscillators and SRAM—Moving to Circuit Implementation
The team describes its latest achievement as creating the “building blocks” for future logic devices. The next challenge is transforming those building blocks into fully functioning circuits.
Q. What are the team’s next research goals?
“This research demonstrated we could vertically stack n-type and p-type transistors (the two core components that handle current switches in opposite directions). In construction terms, we have successfully manufactured the brick.
Now, we need columns and frames to build a functional house. Our next step is to construct a ‘Ring Oscillator’ (a test circuit used to verify operational integrity) and ‘SRAM’ blocks (a high-speed temporary memory circuit). These structures will allow us to verify whether electrical signals flow properly, whether logic operations remain stable and whether data can be reliably stored and retrieved. By successfully demonstrating these circuit-level building blocks, we aim to take the next step toward actual chip production.”
— WookHyun Kwon, Master, Logic Technology Development Team, Samsung Electronics Semiconductor R&D Center
Samsung Semiconductor R&D Center’s Logic TD Team emphasized that this 42nm gate pitch 3D Stacked FET milestone marks an important step in logic chips moving beyond the limits of two-dimensional scaling and into the vertical dimension. The path toward smaller, faster and more powerful semiconductors is now extending into the vertical dimension.
(Note: This article was adapted from a written interview with the Logic TD Team at Samsung Semiconductor R&D Center.)
For more in-depth explanation of the technical aspects of the paper, please visit the Samsung Semiconductor Tech Blog on the official website.
[1] Transistor: A semiconductor device used to amplify or switch electrical signals. As the fundamental building block of modern digital circuits, with leading-edge chips integrating tens of billions of transistors on a single die.
[2] Gate Pitch: The center-to-center spacing between adjacent transistor gates. A smaller gate pitch allows more transistors to be integrated within the same chip area, making it a key indicator for transistor density and scaling.
[3] Aspect Ratio: The ratio of a structure’s height to its width. In 3D stacked structures, a higher aspect ratio drastically increases the difficulty of etch and deposition processes.
[4] RBC (RX Bounded Contact): A vertical contact scheme that directly connects upper and lower transistors. While more process-challenging than the traditional wrap-around contact method, it is highly advantageous for scaling down the device footprint.
